1. Field of Invention
This invention relates to a system for executing operation code in an order different from that in which it is received and more particularly in such a system in a pipeline parallel processor.
2. Description of the Prior Art
Prior art data processors have in general been sequential in nature due to the sequential nature of the conventional imperative code they employ. A particulary processor module of this type is disclosed in the Barton, et al. U.S. Pat. Nos. 3,461,434; 3,546,677 and 3,548,384. These patents are directed toward a stack oriented data processor where the function of the stack mechanism, a first-in last-out mechanism, is to handle the flow of operators and associate parameters in a manner which reflects the nested structure of particular higher level languages. However, where it is desired to provide a customer with an upgrade for such a processor, it becomes necessary to increase the throughput of the processor while maintaining program compatability with previous and smaller members of the same processing family.
The execution of a sequence of code involves three basic forms of processing: the processing of the instruction format, the processing of references created by that instruction and the execution of the function specified by the instruction. In a simple sequential machine, the total time to execute a sequence So; . . . Sn is (Io+Ro+Ro)+ . . . (In+Rn+En) where I is an instruction processing, R is a referencing processing and E is an execution processing. In a simpler pipeline machine, ignoring certain dependencies, the same sequence can be executed in a time equal to the largest sum of processing stage, namely (Io+Ii+ . . . In) and so forth where the individual instruction processing, reference processing and execution processing are done in parallel. Such a parallel pipeline processor (as distinct from a parallel processing array) is disclosed in the Reynard et al. patent application U.S. Ser. No. 625,612, filed June 28, 1984, and assigned to the same assignee as the present invention.
The above described Reynard et al. application is directed towards a specific invention that is not directly related to the present application. However, in prior art parallel processors of the type described in that application, the incoming code stream is received by a program control unit which then generates operation codes, addresses and other parameters for transmission to an execution unit and a memory referencing unit for concurrent execution. These units receive their designated operators and so forth in respective queues for evaluation or execution in a pipeline manner. Such a pipeline is normally sequential in nature, particularly in the memory referencing unit, and greater concurrency can be achieved by executing a class of reference operations out of order with respect to the code stream, subject to certain limitations.
It is then an object of the present invention to provide an improved pipeline processor having increased concurrency of operation execution.
It is another object of the present invention to provide an improved parallel pipeline processor having concurrence in the reference pipeline of the memory address formation unit of the processor.
It is still another object of the present invention to provide improved concurrency in a pipeline processor by executing a class of reference operations out of order with respect to the incoming code stream.